Early IP Block Error Detection is Critical!
The rising complexity of modern SoC designs, as enabled by progressing manufacturing technology, leads to an increasing validation challenge as the only way to manage complexity increase is by re-using more pre-designed IP blocks. These IP-blocks are provided by various suppliers such as a foundry partner, internal design groups, open-source IP and third-party IP companies. This is driving the trend of increasing IP Qualification costs, which is part of an exponential growth of total SoC design cost.
Cost in terms of IP qualification and design-verification is mostly found in design-time spent in verification runs and resolving the issues found. A well-known design principle is that the closer an error is detected to its point of creation, the less costly fixing it becomes. That is why design-teams deploy various techniques before accepting an IP block into their SoC design flow. Any issue found during IP qualification or incoming inspection, can be directly fixed within the IP by the IP supplier. Failing early detection, design teams are faced with the tedious path of tracing an issue in the final design back to a single IP block. After which of course the IP still needs to be repaired, re-released and re-integrated in the final design.IP qualification methods have evolved from self-certified questionnaires, through home-grown IP qualification scripting into an industry-standard IP qualification solution known as Fractal Crossfire.
An IP qualification solution will certify that an IP release is complete, has internal consistency and will exhibit predictable trends within and over characterization corners. All these are must-have properties for an IP block before it can be included in any SoC design.We argue that for a design-team that is approaching tape-out, having the IP qualified is necessary, but not enough. In the scenario where a design-team is receiving regular incremental revisions of an IP block, it is also essential that these revisions gradually converge to a steady state where changes to the IP block are limited to only the bare minimum. If in a late stage of the design an IP block is shipped that has a large delta with respect to the previous release, this can pose a huge risk to the final design schedule, even when the IP is successfully qualified.