Response to IP's Growing Impact On Yield And Reliability
One of the reasons I founded SemiWiki nine years ago was the lack of EDA, IP and Foundry content in the media. The problem is that unless you work in the industry it is very difficult to write about it in competent technical detail. Most media outlets only know what vendors tell them which is how the semiconductor industry worked before social media (blogging) came into power.
Interview EDACafe with Felipe Schneider
Interview EDACafe with Felipe Schneider - Director, Field Operations at Fractal Technologies.
Fractal at TSMC 2019 OIP Ecosystem forum
Visit us at booth 916 for the latest Crossfire update at TSMC Technology Symposium.
Early IP Block Error Detection is Critical!
The rising complexity of modern SoC designs, as enabled by progressing manufacturing technology, leads to an increasing validation challenge as the only way to manage complexity increase is by re-using more pre-designed IP blocks.
Driving a Global EDA Industry Transcendence
Fractal Technologies Inc.: Driving a Global EDA Industry Transcendence.
Fractal at TSMC 2019 Technology Symposium
Visit us at booth 207 for the latest Crossfire update at TSMC Technology Symposium.
Fractal at Design Automation Conference (DAC)
Visit us for the latest Crossfire update at DAC 2019, Las Vegas, NV, June 2-6
Recent Crossfire improvements
Top 10 IP Solution providers 2019
Fractal Technologies recognized by Embedded Advisor Magazine as Top 10 IP Solution providers 2019!
The Silicon Review: 50 leading companies of 2018
We are the first company in the market with a commercial tool for IP validation and we deliver what we promise.
IP & Library QA with Crossfire presentation
Register here to watch recorded presentation!
Crossfire Baseline Checks for Clean IP Part II
In our previous article bearing the same title, we discussed the recommended baseline checks covering cell and pin presence, back-end, and some front-end checks related to functional equivalency. In this article, we'll cover the extensive list of characterization checks, that include timing arcs, NLDM, CCS, ECSM/EM, and NLPM.
Fractal Technologies listed on TOP 20
We are very proud to be part of the TOP 20 IP design and solution provider published in embedded advisor! IC designs are becoming incredibly complicated and with the shrinking design cycle to ensure time to market, semiconductors companies are heavily relying on internal and external Silicon IPs.