News


  • Siemens expands industry-leading IC verification portfolio with acquisition of Fractal Technologies

    Siemens Digital Industries Software today announced that it has acquired Fractal Technologies, a provider of production signoff-quality IP validation solutions, based in the U.S. and the Netherlands. With this acquisition, Siemens' electronic design automation (EDA) customers can more quickly and easily validate internal and external IP and libraries used in their integrated circuit (IC) designs to improve overall quality and speed time to market.

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  • Fractal at GOMACTech 2021

    Visit us at our virtual booth at GOMACTech, March 29 - April 1, 2021!

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  • Samsung Foundry 2020 SAFE Forum

    On October 28 we will participate at the Samsung Foundry 2020 SAFE Forum. During this event, Felipe Schneider, our Director Field Operations North America will show the presentation "Samsung's IP Validation Ecosystem using Fractal's Crossfire".

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  • Interview EDACafe with Felipe Schneider

    Interview EDACafe with Felipe Schneider - Director, Field Operations at Fractal Technologies.

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  • Fractal at virtual event TSMC 2020

    TSMC 2020 | TSMC North America Technology Symposium & OIP Ecosystem Forum | August 24-25

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  • Fractal at virtual event DAC 2020

    DAC 2020 | A Virtual Experience | July 20-24

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  • Fractal CEO Update 2020

    Rene Donkers, the company's Co-founder and CEO, started his EDA career at Sagantec where he became responsible for world wide customer support and operations management. Ten years ago, Rene and a handful of people noticed a need in the design community for a standardized (portable) IP Validation approach to replace internal solutions, and thus Fractal was founded with Rene as the CEO.

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  • Fractal Technologies: Stalwarts of IP Design Validation

    Integrated circuit (IC) designs are becoming extremely challenging owing to the increasing complexity of new process nodes. Since new semiconductor manufacturing nodes does not support the existing IP or library characterization flows, circuit designers are obligated to include new formats and databases in the IP deliverables. Now, to ensure the quality and system reliability of the new process nodes, IP design validation becomes highly essential. As manually checking every cell in a library for its consistency among several data formats, functionalities, and labels is nearly impossible, circuit designers need a dynamic and powerful validation tool.

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  • Why IP Designers Don't Like Surprises!

    If it's your job to get a SoC design through synthesis, timing/power closure and final verification, the last thing you need are surprises in new versions of the IP blocks that are integrated into the design. If your IP supplier sends a new version, the best possible scenario is that this is only a small incremental change from what you had before, fixing only those issues that are in the way of final tape-out.

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  • Fractal at GOMACTech 2020

    Visit us for the latest Crossfire update at GOMACTech 2020, San Diego, CA, March 16-19, 2020.

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  • Fractal at Design Automation Conference (DAC) 2020

    Visit us for the latest Crossfire update at DAC 2020, San Francisco, CA, July 20-22, 2020.

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  • Fractal accepted as partner in the Samsung Foundry SAFE program

    Fractal Technologies is proud to announce they are accepted as a partner in the Samsung Foundry SAFE program. "This is a great achievement for our Crossfire IP Validation solution" says Rene Donkers, CEO of Fractal Technologies. We are very happy Samsung Foundry accepted our application for the Samsung Foundry SAFE program and we are looking forward working with Samsung Foundry and our common customers that will benefit from this partnership.

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  • Response to IP's Growing Impact On Yield And Reliability

    One of the reasons I founded SemiWiki nine years ago was the lack of EDA, IP and Foundry content in the media. The problem is that unless you work in the industry it is very difficult to write about it in competent technical detail. Most media outlets only know what vendors tell them which is how the semiconductor industry worked before social media (blogging) came into power.

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  • Interview EDACafe with Felipe Schneider

    Interview EDACafe with Felipe Schneider - Director, Field Operations at Fractal Technologies.

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  • Fractal at TSMC 2019 OIP Ecosystem forum

    Visit us at booth 916 for the latest Crossfire update at TSMC Technology Symposium.

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  • Early IP Block Error Detection is Critical!

    The rising complexity of modern SoC designs, as enabled by progressing manufacturing technology, leads to an increasing validation challenge as the only way to manage complexity increase is by re-using more pre-designed IP blocks.

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  • Driving a Global EDA Industry Transcendence

    Fractal Technologies Inc.: Driving a Global EDA Industry Transcendence.

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  • Fractal at TSMC 2019 Technology Symposium

    Visit us at booth 207 for the latest Crossfire update at TSMC Technology Symposium.

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  • Fractal at Design Automation Conference (DAC) 2019

    Visit us for the latest Crossfire update at DAC 2019, Las Vegas, NV, June 2-6 2019

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  • Crossfire updates

    Recent Crossfire improvements

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  • Top 10 IP Solution providers 2019

    Fractal Technologies recognized by Embedded Advisor Magazine as Top 10 IP Solution providers 2019!

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  • The Silicon Review: 50 leading companies of 2018

    We are the first company in the market with a commercial tool for IP validation and we deliver what we promise.

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  • IP & Library QA with Crossfire presentation

    Register here to watch recorded presentation!

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  • Crossfire Baseline Checks for Clean IP Part II

    In our previous article bearing the same title, we discussed the recommended baseline checks covering cell and pin presence, back-end, and some front-end checks related to functional equivalency. In this article, we'll cover the extensive list of characterization checks, that include timing arcs, NLDM, CCS, ECSM/EM, and NLPM.

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  • Fractal Technologies listed on TOP 20

    We are very proud to be part of the TOP 20 IP design and solution provider published in embedded advisor! IC designs are becoming incredibly complicated and with the shrinking design cycle to ensure time to market, semiconductors companies are heavily relying on internal and external Silicon IPs.

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