Crossfire baseline checks

Standard cell library, IO and Hard IP validation tool

Crossfire supports over 30 standard design formats, from front-end to back-end, including simulation and schematic views, binary databases such as Milkyway, OpenAccess, and NDM, documentation, and custom formats such as Logic Vision and Ansys APL. Any other ASCII based custom formats can also be easily integrated into the tool. The recommended baseline of checks can be separated into three sections: cell and pin presence for all formats, back-end checks, and front-end related checks.

1. Cell and Pin Presence Checks

Although consistency checks such as cell and pin presence may sound trivial, and for the most part they are, one cannot sweep such important tasks under the rug. Don’t be surprised if an IP or standard cell library from a well-known IP vendor is delivered with inconsistencies between the various formats, including cell and pins names, port direction, and hierarchy differences.

2. Back-end Checks

Ensuring layout related consistencies across all back-end related formats is an important part of the IP QA qualification. Pin labels and shape layers must match across all layout and abstract formats. All layout formats such as GDS, Oasis, Milkyway CEL, NDM and OpenAccess layout views must directly match across the board. When comparing a layout to an abstract format such as LEF, Milkyway FRAM or NDM frame, one must ensure that all layer blockages correctly cover un-routable areas in the layout. On top of that, pin shapes and layers must match in order to guarantee a clean DRC/LVS verification down the line.

Other important checks to consider include area attribute definitions for non-layout formats which must match the area defined by the boundary layers for various layout formats. IP and standard cell pins must be accessible by the router and for non-standard cell related IP, pin obstruction needs to be checked in order to ensure accessibility. In some cases, ensuring that all pins are on a pre-defined grid can also be a necessary task. In the end, these checks will ensure a quicker and less error-prone P&R execution.

3. Front-end Checks

Front-end checks can be broken into seven separate sections: functional characterization, functional verification, timing arc, NLDM, CCS, ESCM/EM, and NLPM.

3.1. Functional Characterization Checks

Functional characterization checks ensure the timing arcs are defined correctly when compared the given Boolean functions for formats like Liberty, Verilog, and VHDL. Other checks include power down function correctness, ensuring related power and ground pins are defined correctly when compared to spice netlists or UPF models (correct pins are extracted from spice by traversing the circuits defined in the spice format). We also recommend checking related bias pins and whether input pins are correctly connected to gate or antenna diodes.

3.2. Functional Verification Checks

When dealing with standard cell libraries, it is important to establish the Boolean equivalence of all formats that describe the behavior of a cell. This will ensure that all formats behave in the same manner when dealing with functionality during various front-end related timing simulations.

3.3. Timing Arc Checks

The recommended timing arc checks should include checking equivalence of WHEN and SDF conditions in a given liberty file, condition consistencies across different timing corners, and Liberty vs. Verilog/VHDL arc consistencies. This is essential in order to ensure accurate digital simulations and timing analysis.

3.4. NLDM Characterization Checks

NLDM related characterization QA should include consistency checks between delay and transition tables, ascending capacitance and transition index values, correct number of indices, and range checks for delay, transition, setup/hold, and minimum period. Ensuring that cell rise and fall delay values don’t vary too much can be a valuable check for clocks, as well as other ports that may require a balanced delay.

It may also be prudent to ensure delays increase with increasing output capacitance, input transition times, and decreasing supply voltage. At the same time, checking that both transition and capacitance values don’t fall outside the range of the defined maximum transition and capacitance is also a necessity. This will ensure that no extrapolation is needed when characterized data is used in a design flow environment. In terms of transition trip points, one must ensure that they are symmetrical and must be a given percentage outside of the delay trip points. Other accuracy checks should include checking for non-changing or zero delay or transition values in a given table.

When comparing two or more PVT corners, large delay deviations should be closely monitored, exact values should not repeat, pin properties and parameters should be consistent, and mode definitions should match. Capacitance and transition properties should be consistently defined for all pins. More importantly, ensuring the same tables and arcs are defined across all given corners will provide a more stable and error-free timing analysis down the line.

Constraint values and related timing information such as setup and hold tables should be defined in matching pairs. Each matching setup and hold tables should have equal indices, and the sum of setup and hold values should be greater than zero. For clock related pins, ensuring pulse width definitions is also necessary.

Additional consistency checks should flag cases where duplicated or illegally defined parameters are used and ensure user-defined parameters are correct. Temperature, voltage, and process corner parameters should be consistent with the library and file name. On top of this, units must be consistent and defined as expected. Pin related checks should guarantee the presence of arcs and the use of required tables and omission of obsolete ones. An important, yet often overlooked check, should ensure that related pin terminals are not defined as outputs.

For standard cell libraries, cell to cell trends with respect to changes related to increasing output drive should be closely monitored. They include area, cell footprint, pin attributes, arc consistency, delay, and power monotonicity. Also, ensuring consistency among the attributes pertaining to power switch cells and its pins will guarantee correct usage of specific cells.

On-chip variation related timing checks should include table presence, monotonicity, and guarantee that all files are paired correctly (when comparing NLDM to AOCV/POCV files).

3.5. CCS Characterization Checks

Many of the checks explained above also apply for newer technologies where CCS (Composite Current Source) timing is needed. Additionally, checking for multiple peaks in a waveform plot, current deviations above the absolute current tolerance value, and ensuring that current values don’t increase with output capacitance, is a must. Delay and transition values measured from the current waveforms should be within a specified percentage of those characterized in NLDM tables.

For noise related characterization, the data related to CCS-noise modeling must respect the Liberty CCSN specifications. In particular, one must ensure that DC current and propagated noise tables (within first/last stages) have valid indices and values. Additionally, one should ensure the output voltages and propagated noise values are also within defined ranges.

CCS power characterization can also benefit from many of the above checks along with ensuring that all given templates follow the Liberty specification guidelines. The nominal voltage must match the operating condition voltage. This is essential is guaranteeing correct data for a given voltage corner. The dynamic current group must be present for all cells and for power pins, the current must be positive, and negative for ground pins. Additionally, the reference time must be greater than zero since it’s related to physical circuit behavior. The same checks also apply to leakage current. In the absence of gate leakage values, current conservation must hold within the same leakage current group. If all power and ground pins are specified with leakage currents, the sum of all currents should be zero. Finally, when dealing with intrinsic resistance, total capacitance, or intrinsic capacitance, values should not be negative or zero.

3.6. ECSM/EM Characterization Checks

Effective Current Source Model (ECSM) and Electro-Migration (EM) related checks are in line with those specified for CCS. Beside ensuring that all tables are consistent across all corners, current values must also be checked to ensure monotonicity across given capacitive loads. Checking for the presence of a given combination of average, peak, and RMS current types may be a design specific requirement that would need to be qualified as well.

3.7. NLPM Characterization Checks

Last, but not least, power related characterization checks should include the standard and expected trends related to capacitance, transition times, and voltage. Power is expected to increase when load capacitance or transition times increase. At the same time, it is expected to decrease when supply voltages decrease. In terms of leakage power, one might want to ensure that values fall within an expected range and check whether pins are correctly defined for a given condition, whether they are required or missing.